1. Field of the Invention
The present invention relates to an information processing apparatus for performing calculation processing for data such as an image stored in a memory at high speed, a control method for the information processing apparatus and an electronic device.
2. Description of the Related Art
Conventionally, there are known an information processing method and information processing apparatus which perform, for an array of a number of element data items such as images stored in a memory, calculation processing by sequentially referring to element data at specific positions according to a predetermined rule, and obtain a calculation result.
A method which uses a Boosting type discriminator for detecting a target object such as a human face in image data at high speed is proposed in, for example, “Rapid Object Detection using a Boosted Cascade of Simple Features”, P. Viola and M. Jones, IEEE Conference on Computer Vision and Pattern Recognition 2001 (to be referred to as reference 1 hereinafter). This method accumulates scores obtained by sequentially referring to and calculating feature amounts at predetermined positions within a sliding window based on the dictionary of cascaded weak discriminators, which has been obtained in advance by machine learning, and then determines whether to abort calculation or the object is a final target object.
A Haar-like feature calculated as the linear sum of total values within a plurality of local rectangles is used as a feature amount referred to by each weak discriminator. It is possible to calculate, with a low load, a total value within a rectangle by performing addition/subtraction processing by referring to only four points in an integral image or an image called a summed area table, which has been generated in advance from an original brightness image.
As a feature amount to be referred to by each weak discriminator, a feature amount which maximizes the discrimination performance when the weak discriminator is executed is selected by pre-learning using a number of sample data items. Furthermore, if an accumulated score obtained by adding a score so far to a score calculated by the weak discriminator has not reached a predetermined threshold, subsequent calculation is aborted to reduce the overall calculation amount, thereby increasing the speed.
Japanese Patent No. 4553044 (to be referred to as reference 2 hereinafter) realizes high-speed recognition processing by a number of weak discriminators similar to those described in reference 1 by using, as a feature amount, the difference in brightness between two points determined by pre-learning for each weak discriminator in a discrimination target brightness image.
There is also proposed a method for realizing multi-class discrimination at high speed with high accuracy by creating a multi-class discriminator by combining a number of nodes each of which performs binary discrimination by simple calculation. For example, a method called randomized trees described in “Keypoint recognition using randomized trees”, V. Lepetit and P. Fua, IEEE Transaction on Pattern Analysis and Machine Intelligence, 28(9): 1465-1479, September 2006 (to be referred to as reference 3 hereinafter) uses a discriminator obtained by combining a number of nodes in a binary tree pattern, thereby omitting unnecessary discrimination. Furthermore, a method called random ferns described in “Keypoint recognition using Random Ferns”, M. Ozuysal, M. Calonder, V. Lepetit, and P. Fua, IEEE Transaction on Pattern Analysis and Machine Intelligence, 32(3): 448-461, March 2010 (to be referred to as reference 4 hereinafter) uses a discriminator which uses a single binary feature within a single hierarchical layer, thereby proposing a higher-speed multi-class discriminator.
As described above, in many conventional information processing methods of performing discrimination processing for, for example, an image, attention is paid to only reduction in calculation amount of a discriminator to increase the speed.
On the other hand, there are various kinds of memory architectures for the circuit of a processing system such as a computer for executing such information processing. For example, in general, an architecture including a DRAM which has a large capacity but takes long time to access from a processor and an SRAM which is arranged near the processor and can be accessed at high speed but has a small capacity has been often used.
Some of such architectures increase the speed by transferring a continuous area with a predetermined size at once from the DRAM to the SRAM, which is called burst transfer.
Alternatively, a cache mechanism in which a predetermined range is copied to the SRAM when accessing data in the DRAM and then only the SRAM is accessed when referring to data within that range has been often used. Various schemes such as a direct mapping scheme and set associative cache are proposed as cache mechanisms.
To perform calculation processing for data at high speed, it is effective to reduce, as much as possible, not only a calculation amount but also a load (to be referred to as a reference load hereinafter) generated in data access, in addition to consideration of a memory architecture as described above.
In Japanese Patent Laid-Open No. 2010-102584 (to be referred to as reference 5 hereinafter), discriminators are divided into a first half group and a second half group, and a local feature referred to by a discriminator in the first half group is limited to a long linear shape in the main scanning direction. Alternatively, a local feature is selected by limiting to pixels within a range obtained by thinning out pixels every other line. This facilitates burst transfer from the DRAM to the SRAM, thereby attaining high speed.
Japanese Patent Laid-Open No. 2005-190477 (to be referred to as reference 6 hereinafter) describes processing of performing discrimination processing for each block of an image by referring to a histogram corresponding to a discrimination processing dictionary. Changing the order of bins of a histogram from the normal order improves a cache hit rate when referring to the histogram.
The techniques disclosed in references 1 to 4 do not consider the memory architecture of a processing system for executing information processing. The technique disclosed in reference 5 mainly pays attention to burst transfer, and does not directly consider a cache architecture. The technique disclosed in reference 6 improves the cache hit rate when referring to a histogram generated in advance, that is, discrimination processing dictionary data for object detection processing but does not consider reference to processing target image data.